1. Field of the Invention
The present invention relates to a semiconductor integrated circuit on which an SRAM or other memory and a logic circuit are mounted together.
2. Description of the Related Art
A semiconductor integrated circuit of a type called a system on chip (SoC), wherein a function block divided to a plurality of semiconductor chips are integrated on one semiconductor chip, has emerged as the processing dimensions of a semiconductor circuit have become finer.
Particularly, in recent years, in the field of portable electronic equipment which is highly demanding in terms of the size and costs, a semiconductor integrated circuit wherein a high speed memory, such as a SRAM and a DRAM, and a logic circuit are mounted together has come to be widely used.
On the other hand, however, due to the processing dimensions becoming finer and the integrated rate becoming improved, it has become extremely difficult to produce all the bits of a semiconductor memory without any defects. Therefore, an effective test for finding a defect in memories mounted on the semiconductor integrated circuit has been desired.
Generally, a scan test is known as a testing method of a logic circuit of a semiconductor integrated circuit.
In a semiconductor integrated circuit for carrying out the scan test, a shift register called a scan path circuit is mounted in advance. The scan path circuit is connected to an input or output of a logic circuit to be tested and allows an input/output signal of the logic circuit to pass through in a normal operation, so that it does not affect a logical function. On the other hand, when carrying out a scan test, the scan path circuit latches a test pattern serially transferred from the outside of the semiconductor integrated circuit and inputs the same to the logic circuit to be tested. Then, the scan path circuit retrieves a signal output from the logic circuit in accordance with the test pattern and serially transfers the same to the outside of the semiconductor integrated circuit.
In the scan test method as above described, a test pattern has to be serially transferred every time to obtain one test result (a set of input data and output data), so that when it is applied to a test of a mixed mounted memory on the semiconductor integrated circuit, it brings a disadvantage that the test time becomes very long.
Thus, a method of mounting a memory testing circuit inside the semiconductor integrated circuit in advance to generate a test pattern and conduct a test of output data in the testing circuit is normally used. The method of mounting a self testing circuit inside the semiconductor integrated circuit is generally called a built in self test (BIST).
FIG. 9 is a view of an example of the configuration of a semiconductor integrated circuit of the related art, wherein a plurality of memory units and the testing circuits are mounted together.
The semiconductor integrated circuit shown in FIG. 9 has memory test blocks 101, 102 and 103 as circuit blocks relating to the memory test.
The memory test blocks 101 to 103 respectively include a memory unit MEM 101, such as a SRAM, logic circuits LG101 and LG102 connected to an input and output of the memory unit MEM1, scan flip-flops SF101, . . . , SF110, selectors SEL101, . . . , SEL105, and a memory testing circuit BT101.
At a normal operation, the memory unit MEM101 receives as an input an output signal of the logic circuit LG101 (write data DIN, address data ADR, a chip selection signal CS and a read/write selection signal RW) via the selectors SEL101 to SEL104. Also, read data DOUT of the memory unit MEM101 is output to the logic circuit 102 via the selector SEL105.
The scan flip-flops SF101 to SF110 and other not shown scan flip-flops compose a scan path circuit.
When carrying out a scan test, the logic circuit LG101 receives as an input data to be set to the scan flip-flops SF101 to SF104. Data to be set to the scan flip-flops SF109 is input to the logic circuit LG102 via the selector SEL105.
Then, output data of the logic circuit LG101 in accordance with the testing input data is retrieved by the scan flip-clops SF105 to SF108 via the selectors SEL101 to SEL104. Output data of the logic circuit LG102 is retrieved by the scan flip-flop SF110.
On the other hand, when testing a memory, the memory unit MEM101 receives as an input a test pattern (write data DIN, address data ADR, a chip selection signal CS, and a read/write selection signal RW) generated by the testing circuit BT101 via the selectors SEL101 to SEL104. Then, a read data DOUT of the memory unit MEM101 in accordance with the test pattern is input to the testing circuit BT101 via the selector SEL105. In the testing circuit BT101, a test for detecting a defect in the memory unit MEM101 is conducted based on the input read data DOUT.
A test result S103 of the testing circuit BT101 in each memory test block (101 to 103) is retrieved by an external testing device of the semiconductor integrated circuit and used for analyzing detects of the memory unit, etc.
As explained above, in the semiconductor integrated circuit of the related art shown in FIG. 9, the testing circuit BT101 is provided for each memory test block (101 to 103), so that an increase of the circuit area due to the testing circuits BT101 becomes a problem.
Particularly, in recent years, defect modes of a memory have become diverse due to a semiconductor circuit becoming finer and requiring a lower voltage. Namely, there are a mode of causing a defect collectively by adjacent memory cells and a mode of causing defects separately by memory cells in a way of scattering to spots, etc. Therefore, it has become difficult to detect defects sufficiently by a simple test pattern.
As a result, the memory testing circuit incorporated in the semiconductor integrated circuit in the BIST method is demanded to generate a detailed test pattern capable of dealing with a variety of defect modes and to have a high testing ability to process a large number of test results obtained in accordance therewith.
Such a high-performance testing circuit requires a large number of circuit elements, so that when it is applied to the method of providing a testing circuit for each memory to be tested as explained above, there arises a disadvantage that the circuit area remarkably increases.
To suppress the increase of the circuit area by the testing circuits, for example, as shown in FIG. 10, a method of using a test circuit in common by a plurality of memory test blocks can be also considered.
The semiconductor integrated circuit shown in FIG. 10 has memory test blocks 104, 105 and 106.
The memory test blocks 104 to 106 are obtained by omitting the testing circuit BT101 from the memory test blocks 101 to 103 explained above.
A test of the memory unit MEM101 in the memory test blocks 104 to 106 is conducted by a common testing circuit BT102.
However, the method of sharing a testing circuit as shown in FIG. 10 has a disadvantage that the test speed declines due to a wiring delay between a memory and the testing circuit.
Namely, when the number of memories increases, a wiring length from a memory to the testing circuit becomes long and a parasitic capacitance of the wiring generates a signal delay, so that the test speed becomes slow. Therefore, the number of memories to share a testing circuit has to be limited to keep the decline of the testing speed within an allowance. Accordingly, when the number of memories is large or operation speeds of memories are high, a plurality of testing circuits has to be provided and an increase of the circuit area becomes a hurdle.